Level meter circuit

ABSTRACT

A level meter circuit for displaying the level of an input signal by the use of a number of light emitting diodes. The circuit has a parallel circuit of a plurality of unit circuits each having a diode circuit and a current control transistor connected in series with the parallel circuit and controlled by the input signal, the level of which is to be displayed. In accordance with the input signal level to be displayed, one or more of the diodes are activated to emit light, thus providing a display of the input signal level.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a level meter circuit for displaying the level of an input signal by the use of a number of light emitting diodes.

2. Description of the Prior Art

Therefore there have been proposed various level meter circuits of the type displaying the input level through utilization of a large number of light emitting diodes. One of such conventional level meter circuits has a number of comparators respectively corresponding to the light emitting diodes and a number of reference signal sources respectively corresponding to the comparators. The light emitting diodes are each driven by one of the comparators corresponding thereto. The comparators each compare the output from one of the reference signal sources corresponding thereto and the input signal the level of which is to be displayed. The level of the input signal is displayed by lighting those of the light emitting diodes which correspond in number to the input signal level.

As noted above such a prior art level meter circuit calls for comparators and reference signal sources of the same number as the light emitting diodes used, and hence it has the defects of bulkiness, complexity and expensiveness.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a novel level meter circuit which is free from the abovesaid defects of the prior art.

According to the present invention, the level meter circuit is provided with a parallel circuit of a plurality of unit circuits and current control means, such as a transistor, which is connected in series with the parallel circuit and controlled by the input signal the level of which is to be displayed. The unit circuits each has a diode circuit, which is composed of a plurality of series-connected diodes and current bypass resistors, each connected in parallel with one of the diodes. The unit circuits except one of them are each provided with current detecting means, such as a resistor, which is connected in series with the diode circuit. Further, the unit circuits except another one of them are each provided with current control means, such as a transistor, which is connected in series with the diode circuit and controlled by the current detecting means. In accordance with the input signal level to be displayed, one or more of the diodes are activated to emit light, thus providing a display of the input signal level.

Accordingly, the level meter circuit of the present invention is able to display the input signal level with a simple circuit arrangement and does not require the utilization of numbers of comparators and reference signal sources such as have been employed in the aforementioned conventional level meter circuit. Therefore, the level meter circuit of the present invention has the advantages of small and simple structure and low manufacturing cost.

Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

The accompanying drawing is a connection diagram illustrating an embodiment of the level meter circuit of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The illustrated embodiment of the level meter circuit has a parallel circuit 1 of a parallel connection of P unit circuits M₁ to M_(P) and a main current control circuit 2 connected in series with the parallel circuit 1. The following description will be given on the assumption that P is an odd number for the sake of simplicity. The one end of the series circuit on the side of the parallel circuit 1 is connected to a positive terminal 4 of a power source 3 and the other end on the side of the main current control circuit 2 is connected via the ground to a negative terminal 5 of the power source 3.

The main current control circuit 2 is supplied, via output terminals 7 and 8 of an input signal source 6, with an input signal S the level of which is to be displayed. The main current control circuit 2 is controlled by the input signal S so that a current I_(S) flowing via the circuit 2 from the power source 3 to the parallel circuit 1 may assume a value (which is identified by the same reference character I_(S) as the current I_(S) for the sake of brevity) corresponding to the level (which is identified by V_(S)). Such a current control circuit 2 may be a known one.

An example of the current control circuit 2 has an NPN type current control transistor 9 of relatively high output impedance. The transistor 9 has its collector connected to one end of the parallel circuit 1 and has it emitter grounded via a resistor 10 and consequently it is connected in series with the parallel circuit 1 via a resistor 10. The input signal source 6 is connected at the one end 7 to the base of the transistor 9 and grounded at the other end 8. The transistor 9 is controlled by the input signal S so that the current I_(S) flowing therethrough to the parallel circuit 1 may take the value I_(S) corresponding to the level V_(S) of the input signal S.

The unit circuit M_(i) (i=1, 2, . . . P) has a diode circuit G_(i).

The unit circuits M₁ to M.sub.(P-1) except the circuit M_(P) respectively have current detecting circuits F₁ to F.sub.(P-1) which are connected in series with the diode circuits G₁ to G.sub.(P-1), respectively. The current detecting circuits F₁, F₃, F₅, . . . F.sub.(P-2) are respectively connected in series with the diode circuits G₁, G₃, G₅, . . . G.sub.(P-2) on the opposite side from the main current control circuit 2 and the current detecting circuits F₂, F₄, F₆, . . . F.sub.(P-1) are respectively connected in series with the diode circuits G₂, G₄, G₆, . . . G.sub.(P-1) on the side of the main current control circuit 2.

The unit circuits M₂ to M_(P), other than that M₁, respectively have current control circuits H₂ to H_(P) which are connected in series with the diode circuits G₂ to G_(P), respectively. The current control circuits H₂, H₄ . . . H.sub.(P-1) are respectively connected in series with the diode circuits G₂, G₄, G₆, . . . G.sub.(P-1) on the opposite side from the main current control circuit 2. The current control circuits H₃, H₅, H₇, . . . H_(P) are respectively connected in series with the diode circuits G₃, G₅, G₇, . . . G_(P) on the side of the main current control circuit 2.

The unit circuit M_(i) has a light emitting diode D_(i0) connected in series with the diode circuit G_(i). The diode D₁₀ is connected in series with the diode circuit G₁ on the side of the main current control circuit 2 and the diodes D₃₀, D₅₀, D₇₀, . . . D_(P0) are respectively connected in series with the diode circuits G₃, G₅, G₇, . . . G_(P) on the side of the main current control circuit 2. The diodes D₂₀, D₄₀, D₆₀, D.sub.(P-1)0 are respectively connected in series with the diode circuits G₂, G₄, G₆, . . . G.sub.(P-1) on the opposite from the main current control circuit 2. In this case, the diodes D₁₀, D₃₀, D₅₀, . . . D_(P0) have their cathodes on the side of the main current control circuit 2 and the diodes D₂₀, D₄₀, D₆₀, . . . D.sub.(P-1)0 have their anodes on the side of the power source 3.

Accordingly, in the unit circuit M₁ there are connected in series the current detecting circuit F₁, the diode circuit G₁ and the diode D₁₀ are connected in this order from the side opposite from the main current control circuit 2. Therefore, the current I₁ flows from the power source 3, to the current detecting circuit F₁, the diode circuit G₁ and the diode D₁₀ as a current which is provided via the unit circuit M₁ to the main current circuit 2. In the unit circuits M₁ to M.sub.(P-1), there are respectively connected in series the the diodes D₁₀ to D.sub.(P-1)0, the current control circuits H₁ to H.sub.(P-1), the diode circuits G₁ to G.sub.(P-1) and the current detecting circuits F₁ to F.sub.(P-1) in this order from the side opposite from the main current control circuit 2. Therefore, the currents I₁ to I.sub.(P-1) respectively flow from the power source 3 to the diodes D₁₀ to D.sub.(P-1)0, the current control circuits H₁ to H.sub.(P-1), the diode circuits G₁ to G.sub.(P-1) and the current detecting circuits F₁ to F.sub.(P-1) as currents which are respectively provided via the unit circuits M₁ to M.sub.(P-1) to the main current control circuit 2. In the unit circuit M_(p) there are connected in series the diode circuit G_(P), the current control circuit H_(p) and the diode D_(P0) in this order from the side opposite from the main current control circuit 2. Therefore, the current I_(P) flows from the power source 3 to the diode circuit G_(P), the current control circuit H_(P) and the diode D_(P0) as a current which is provided via the unit circuit M_(P) to the main current control circuit 2. The current detecting circuits F₁ to F.sub.(P-1) of the unit control circuits M₁ to M.sub.(P-1) detect the value of the currents I₁ to I.sub.(P-1) (which values are respectively identified by the same I_(K) to I.sub.(P-1) as the current I₁ to I.sub.(P-1) for the sake of simplicity) and respectively provide the detected outputs as control signals B₁ to B.sub.(P-1).

The current control circuits H₂ to H_(P) of the unit circuits M₂ to M_(P) are respectively controlled by the control signals B₁ to B.sub.(P-1) from the current detecting circuits F₁ to F.sub.(P-1).

Assume that the level V_(S) of the input signal S from the input signal source 6 assumes values V_(S0), V_(S1), V_(S2), . . . V_(SP). Let it be assumed in this case, that the levels V_(S0), V_(S1), V_(S2), . . . V_(SP) bear the following relationships:

    V.sub.S0 (=0)<V.sub.S1 <V.sub.S2 < . . . <V.sub.S(p-1) <V.sub.SP . . . (1)

    |V.sub.S0 -V.sub.S1 |≅|V.sub.S1 -V.sub.S2 |≅ . . . ≅|V.sub.S(P-1) -V.sub.SP |≅V.sub.a . . .              (2)

Let I_(S0), I_(S1), I_(S2), . . . I_(SP) represents the levels of the current I_(S) which flows in the parallel circuit 1 and the current control circuit 2 when the input signal S assumes the levels V_(S0), V_(S1), V_(S2), . . . V_(SP), respectively. Assume, in this case, that the levels I_(S0), I_(S1), I_(S2), . . . I_(SP) bear the following relationships:

    I.sub.S0 (=0)<I.sub.S1 <I.sub.S2 < . . . I.sub.S(P-1) <I.sub.SP . . . (3)

    I.sub.S0 -I.sub.S1 |≅|I.sub.S1 -I.sub.S2 |≅ . . . |I.sub.S(P-1) -I.sub.SP |≅I.sub.a . . .                        (4)

Since the unit circuit M₁ has no current control circuit if the level V_(S) of the input signal S is varied analogously from V_(S0) to V_(SP), the level of the current I_(S) undergoes an analogous change from I_(S0) (=0) to I_(SP).

In the case where the current I_(S) varies analogously from the level I_(SO) (=0) to I_(S1), the current I₁ flowing in the unit circuit M₁ undergoes an analogous change from the level I_(S0) (=0) to I_(S1). In this case, however, the current control circuit H₂ of the unit circuit M₂ is not controlled to be operative by the control signal B₁ from the current detecting circuit F₁ of the unit circuit M₁, so that the current I₂ flowing in the unit circuit M₂ remains at the zero level. Therefore, the currents I₃ to I_(p) of the other unit circuits M₃ to M_(p) also remain at the zero level. That is, in this case, only the current I₁ of the unit circuit M₁ varies from the level I_(S0) to I_(S1), while the currents I₂ to I_(p) of the unit circuits M₂ to M_(p) remain at the zero level.

When the current I_(S) varies analogously from the level I_(S1) to I_(S2), the current I₁ of the unit circuit M₁ is saturated at a level |I_(SO) -I_(S1) |=I_(a). The control circuit H₂ of the unit circuit M₂ is controlled to be operative by the control signal B₁ which is fed from the current detecting circuit F₁ of the unit circuit M₁ in this case. The current control circuit H₂ produces a great change in the level of the current I₂ in response to a very slight change in the level of the control signal B₁. In consequence, the current I₂ of the unit circuit M₂ varies analogously from the level I_(S0) to I_(S1). In this case, however, the current control circuit H₃ of the unit circuit M₃ is not controlled to be operative by the control signal B₂ which is derived from the current detecting circuit F₂ in this case, so that the current I₃ of the unit circuit M₃ remains at the zero level. Accordingly, the currents I₄ to I_(p) of the unit circuits M₄ to M_(P) are also held at the zero level. As a result of this, the current I₁ of the unit circuit M₁ is saturated substantially at the level I_(a) and the current I₂ of the unit circuit M₂ undergoes an analogous change from the level I_(S0) to I_(S1) and the currents I₃ to I_(P) of the unit circuits M₃ to M_(P) are retained at the zero level.

In the case where the current I_(S) changes from the level I_(S2) to I_(S3), the currents I₁ and I₂ of the unit circuits M₁ and M₂ are saturated substantially at the level I_(a). The current control circuits H₃ of the unit circuit M₃ is controlled to be operative by the control signal B₂ from the current detecting circuit F₂ of the unit circuit M₂, causing the current I₃ of the unit circuit M₃ to change analogously from the level I_(S0) to I_(S1). In this case, however, the current control circuit H₄ of the unit circuit M₄ is not controlled to be operative by the control signal B₃ from the current detecting circuit F₃, so that the current I₄ of the unit circuit M₄ remains at the zero level. Accordingly, the currents I₅ to I_(p) of the other unit circuits M₅ to M_(P) also remain at the zero level. As a result of this, the currents I₁ and I₂ of the unit circuits M₁ and M₂ are saturated substantially at the level I_(a) and the current I₃ of the unit circuit M₃ varies from the level I_(S0) to I_(S1) and the currents I₄ to I_(p) of the unit circuits M₄ to M_(P) are held at the zero level.

In the case where the current I_(S) similarly undergo analogous changes from the levels I_(S3) to I_(S4), I_(S4) to I_(S5) . . . I_(S)(P-2) to I_(S)(P-1), the currents I₁ to I₃, I₁ to I₄, . . . I₁ to I.sub.(P-2) of the unit circuits M₁ to M₃, M₁ to M₄ . . . M₁ to M.sub.(P-2) saturated substantially at the level I_(a) and the currents I₄, I₅ . . . I.sub.(p-1) of the unit circuits M₄, M₅ . . . M.sub.(P-1) vary from the level I_(S0) to I_(S1) and the currents I₅, I₆ . . . I.sub.(P-1) of the unit circuits M₅, M₆ . . . M.sub.(P-1) remain at the zero level.

In the case where the current I_(S) varies analogously from the level I_(S5) to I_(S6), the currents I₁ to I.sub.(P-1) of the unit circuits M₁ to M.sub.(P-1) are saturated substantially at the level I_(a) and the current I_(P) of the unit circuit M_(P) varies from the level I_(S0) to I_(S1) .

Further, even if the current I_(S) varies in excess of the level I_(SP), the currents I₁ to I_(p) of the unit circuits M₁ to M_(P) are saturated substantially at the level I_(a).

Specific example of the current detecting circuits F₁ to F.sub.(P-1) of the unit circuits M₁ to M.sub.(P-1) are respectively constituted by resistors R₁₀ to R.sub.(P-1)0 which are connected in series with the diode circuits G₁ to G.sub.(P-1) of the unit circuits M₁ to M.sub.(P-1), respectively. The current control circuits H₂ H₄, H₆, H.sub.(P-1) have, for example, PNP type current control transistors Q₂, Q₄, Q₆, . . . Q.sub.(P-1) of relatively high output impedance, which respectively have their collectors connected to the diode circuits G₂, G₄, G₆, . . . G.sub.(P-)1 at one end thereof, their emitters connected to the cathodes of the diodes D₂₀, D₄₀, D₆₀, . . . D.sub.(P-1)0 and their bases connected to the resistors R₁₀, R₃₀, R₅₀, . . . R.sub.(P-2)0 of the current detecting circuits F₁, F₃, F₅, . . . F.sub.(P-2) on the side of the diode circuits G₁, G₃, G₅, . . . G.sub.(P-2). The current control circuits H₃, H₅, H₇, . . . H_(P) have, for example, NPN type current control transistors Q₃, Q₅, Q₇, . . . Q_(P) of relatively high output impedance, which respectively have their collectors connected to the diode circuits G₃, G₅, G₇, . . . G_(P) at one end thereof, their emitters connected to the anodes of the diodes D₃₀, D₅₀, D₇₀, . . . D_(P0) and their bases connected to the resistors R₂₀, R₄₀, R₆₀, . . . R.sub.(P-1)0 of the current detecting circuits F₂, F₄, F₆, . . . F.sub.(P-1) on the side of the diode circuits G₂, G₄, G₆, . . . G.sub.(P-1). Accordingly, the transistors Q₂ to Q_(P) are respectively connected in series with the diode circuit G_(k) and respectively controlled by the voltage drops across the resistors R₁₀ to R.sub.(P-1)0 of the current detecting circuit F.sub.(k-1). In practice, the resistance values r₁₀, r₂₀, . . . r.sub.(P-1)0 of the resistors R₁₀, R₂₀, . . . R.sub.(P-1)0 bear the following relationships:

    r.sub.10 ≅r.sub.20 ≅ . . . ≅r.sub.(P-1)0 . . .                                                         (5)

The transistors Q₂, Q₄, . . . Q.sub.(P-1) have the same characteristic and the transistors Q₃, Q₅, . . . Q_(p) also have the same characteristic.

The diode circuit G_(i) are provided with plural, N_(i), series-connected light emitting diodes D_(il`), D_(i2), . . . D_(iN).sbsb.i and current bypassing resistors R_(i1), R_(i2), . . . R_(iN).sbsb.i connected in parallel with the diodes D_(i1), D_(i2), . . . D_(iN).sbsb.i, respectively. In this case, the resistance values r_(i1), r_(i2), . . . r_(iN).sbsb.i are suitably selected in such a range that they bear the following relationships:

    r.sub.i1 <r.sub.i2 < . . . r.sub.iN.sbsb.(i-1) <r.sub.iN.sbsb.i . . . (6)

In practice, the numbers N₁, N₂, . . . N_(P) are equal to the diodes D₁₁ to D_(1N), D₂₁ to D_(2N).sbsb.2 . . . D_(P1) to D_(PN).sbsb.P have the same characteristic as the aforesaid diodes D₁₀ to D_(P0). Further, there are the following relationships:

    r.sub.11 ≅r.sub.21 ≅ . . . ≅r.sub.P1 (7)

    r.sub.12 ≅r.sub.22 ≅ . . . ≅r.sub.P2

    r.sub.13 ≅r.sub.23 ≅ . . . ≅r.sub.P3 (7)

In the foregoing, it is described that in the case where the current I_(S) flowing through the parallel circuit 1 changes analogously from level I_(SO) (=0) to the level I_(S1) as the level V_(S) of the input signal S varies analogously from V_(S0) (=0) to V_(S1), the current I₁ of the unit circuit M₁ changes from the level I_(S0) to I_(S1) but the currents I₂ to I_(P) of the unit circuits M₂ to M_(P) remain at the zero level. Consider the case where the input signal S assumes (N₁ +2) levels V_(D0) (=I_(S0)), V_(D1), V_(D2), . . . V_(DN).sbsb.1, V_(D)(N.sbsb.1₊₁) (=V_(S1)) when the input signal level V_(S) varies from V_(S0) to V_(S1). In th is case, let it be assumed that the levels bear the following relationships:

    V.sub.D0 (V.sub.S0 =0)<V.sub.D1 < . . . <V.sub.DN.sbsb.1 <V.sub.D (N.sbsb.1.sub.+1) (=V.sub.S1) . . .                       (8)

    |V.sub.D0 -V.sub.D1 |≅|V.sub.D1 -V.sub.D2 |≅ . . . ≅|V.sub.D(N.sbsb.1.sub.-1) -V.sub.DN.sbsb.1 |≅|V.sub.DN.sbsb.1 -V.sub.D(N+1) |≅V.sub.b . . . (9)

Let I_(D0) (=I_(S0) =0), I_(D1), I_(D2), . . . I_(DN).sbsb.1, I_(D)(N.sbsb.1₊₁) (=I_(S1)) represent the levels of the current I_(S) when the level V_(S) of the input signal S assumes the values V_(D0), V_(D1), . . . V_(DN).sbsb.1, V_(D)(N.sbsb.1₊₁) respectively. In this case, the levels of the current I_(S) bear such relationships as follows:

    I.sub.D0 (=I.sub.SO)<I.sub.D1 <I.sub.D2 <. . . <I.sub.DN.sbsb.1 <I.sub.D(N.sbsb.1.sub.+1) (=I.sub.S1) . . .               (10)

but let it be assumed that they bear the following relationships:

    |I.sub.D0 -I.sub.D1 |≅|I.sub.D1 -I.sub.D2 |≅ . . . ≅|I.sub.D(N.sbsb.1.sub.-1) -I.sub.DN.sbsb.1 |≅I.sub.b . . .                        (11)

When the current I_(S) undergoes an anlogous change from the level I_(DO) (=I_(SO) =0) to the level I_(D1), the current I₁ of the unit circuit M₁ varies analogously from the level I_(DO) (=I_(SO) =0) to the level I_(D1). A current flowing in the diode D₁₀ of the unit circuit M₁ has the same level as does the current I₁ flowing in the unit circuit M₁. The currents flowing in the diodes D₁₁, D₁₂, . . . D_(1N).sbsb.1 have lower levels than the current I₁. The currents flowing in the diodes D₁₁, D₁₂, . . . D_(1N).sbsb.1 become greater in this order. The reason for which such relationship is obtained is that the current bypassing resistors R₁₁, R₁₂, . . . R_(1N).sbsb.1 having the relationships expressed by the equation (6). When the level of the current I₁ becomes I_(D1), the diode D₁₀ is turned ON or lighted but the other diodes D₁₁ to D_(1N).sbsb.1 remain unlighted. In the case where the level of the current I_(S) changes analogously from I_(D1) to I_(D2), the current I₁ also undergoes an analogous change from the level I_(D1) to I_(D2). In this while the diode D₁₀ is supplied with a current which varies analogously from the level I_(D1) to ID₂ but since the level of this current is higher than the level I_(D1), the diode D₁₀ remains lighted. When the level of the current I₁ becomes I_(D2), the diode D₁₁ is lighted but the other diodees D₁₂ to D_(1N).sbsb.1 remain unlighted. In the case where the current I_(S) varies analogously from the level I_(D2) to I_(D3), the current I₁ also varies analogously from the level I_(D2) to I_(D3). In this while the diodes D₁₀ and D₁₁ remain lighted. When the level of the current I₁ becomes I_(D3), the diode D₁₂ is lighted but the other diodes D₁₃ to D_(1N).sbsb.1 are not lighted. Similarly, when the level of the current I_(S) varies analogously from the levels I_(D3) to I_(D4), I_(D4) to I_(D5) . . . I_(D)(N.sbsb.1₋₁) to I_(DN).sbsb.1, the current I₁ also varies analogously from the levels I_(D3) to I_(D4), I_(D4) to I_(D5) . . . I_(D)(N.sbsb.1₋₁) to I_(DN).sbsb.1. In this while the diodes D₁₂, D₁₃ . . . D₁(N.sbsb.1₋₂) keep on lighting. When the level of the current I₁ becomes I_(d4), I_(D5) . . . I_(DN).sbsb.1, the diodes D₁₃, D₁₄ . . . D₁ (N-1) are lighted but the other diodes D₁₄ to D_(1N).sbsb.1, D₁₅ to D_(1N).sbsb.1 . . . D_(1N).sbsb.1 remain unlighted. When the level of the current I₁ becomes I_(D)(N.sbsb.1₊₁) (=I_(S1)), all the diodes D₁₀ to D_(1N).sbsb.1 are lighted.

Consequently, the diodes D₁₀, D₁₁, D₁₂, D₁₃, . . . D_(1N).sbsb.1 of the unit circuit M₁ are sequentially lighted as the level V_(S) of the input signal S varies analogously from V_(S0) to V_(S1).

In the above it is described that in the case where the current I_(S) varies analogously from the level I_(S1) to I_(S2) as the level V_(S) of the input signal S from V_(S1) to V_(S2), the current I₁ is saturated substantially at the level I₁ and the current I₂ of the unit circuit M₂ varies analogously from the level I_(S0) to I_(S1) and the currents I₃ to I_(P) of the unit circuits M₃ to M_(P) remain at the zero level. While the current I₂ of the unit circuit M₂ varies analogously from the level I_(S0) to I_(S1), all the diodes D₁₀ to D_(1N).sbsb.1 of the unit circuit M₁ keep on lighting. When the current I₂ changes analogously from the level I_(S0) to I_(S1), the diodes D₂₀, D₂₁, D₂₂, . . . D_(2N).sbsb.2 of the unit circuit M₂ are lighted in this order. The reason is as follows: The diodes D₂₀, D₂₁, D₂₂, . . . respectively correspond to the diodes D₁₀, D₁₁, D₁₂, . . . of the unit circuit M₁ ; the resistors R₂₁, R₂₂, R₂₃, . . . respectively correspond to the resistors R₁₁, R₁₂, R.sub. 13 . . . of the unit circuit M₁ ; and the analogous variation of the current I₂ of the unit circuit M₂ from the level I_(S0) to I_(S1) corresponds to the analogous variation of the current I₁ of the unit circuit M₁ from the level I_(S0) to I_(S1) in the case where the current I_(S) varies analogously from the level I_(S0) to I_(S1).

Accordingly, when the level V_(S) of the input signal S varies analogously from V_(S1) to V_(S2), the diodes D₂₀, D₂₁, D₂₂, . . . D_(2N).sbsb.2 of the unit circuit M₂ are sequentially lighted in this order, with all the diodes D₁₀ to D_(1N).sbsb.1 of the unit circuit M₁ being lighted.

Similarly, when the level V_(S) of the input signal S varies analogously from V_(S3) to V_(S4), V_(S4) to V_(S5) . . . V_(S)(P-1) to V_(SP), the diodes D₃₀ to D_(3N).sbsb.3, D₄₀ to D_(4N).sbsb.4 . . . D_(PO) to D_(PN).sbsb.p of the unit circuits M₃, M₄ . . . M_(p) are sequentially lighted respectively, with all the diodes (D₁₀ to D_(1N).sbsb.1) to (D₂₀ to D_(2N).sbsb.2), (D₁₀ to D_(1N).sbsb.1) to (D₃₀ to D_(3N).sbsb.3), . . . (D₁₀ to D_(1N).sbsb.1) to (D.sub.(P-1)0 to D.sub.(P-1)N.sbsb.(P-1) of the unit circuits M₁ to M₂, M₁ to M₃, . . . M₁ to M.sub.(P-1) being lighted. When the level V_(S) of the input signal S exceeds V_(SP), all the diodes (D₁₀ to D_(1N).sbsb.1) to (D_(P0) to D_(PN).sbsb.P) of all the unit circuits M₁ to M_(P) are lighted.

Therefore, when the level V_(S) of the input signal S varies analogously from V_(S0) (=0) to V_(SP) or more, the diodes D₁₀, D₁₁, D₁₂, . . . D_(1N).sbsb.1, D₂₀, D₂₁, D₂₂, . . . D_(2N).sbsb.2, D₃₀, D₃₁, . . . D.sub.(P-1)N.sbsb.(P-1), D_(P0), D_(P1), . . . D_(PN).sbsb.P are sequentially lighted in this order. And if the level V_(S) of the input signal S further varies analogously from V_(SP) or more to V_(S0), the diodes D_(PN).sbsb.P, D_(PN).sbsb.(P-1), . . . D_(P0), D.sub.(P-1)N.sbsb.P-1, D.sub.(P-1)(N.sbsb.p-1₋₁), . . . D.sub.(P-1)0, D.sub.(P-2)N.sbsb.(P-2), . . . D_(2N).sbsb.2, D₂ (N₁ -1) . . . D₂₀, D_(1N).sbsb.1, D₁(N.sbsb.1₋₁), . . . D₁₁, D.sub. 10 are sequentially turned OFF in this order.

Accordingly, by arranging the diodes D₁₀, D₁₁, D₁₂ , . . D_(1N).sbsb.1, D₂₀, D₂₁, D₂₂, . . . D_(2N).sbsb.2, D₃₀, D₃₁, D₃₂, . . . D.sub.(P-1)N.sbsb.(P-1) D_(P0), D_(P1), D_(P2) . . . D_(PN).sbsb.P in this order, the diodes of the number counted from the beginning of their arrangement corresponding to the level V_(S) of the input signal S are turned displaying the level V_(S) of the input signal S.

As has been described in the foregoing, the illustrated level meter circuit of the present invention is provided with the parallel connection circuit 1 of the unit circuits M₁ to M_(P) and the main current control circuit 2 which is connected in series with the parallel circuit 1 and controlled by the input signal S. The unit circuit M_(i) has the diode circuit G_(i) provided with the light emitting diodes D_(il) to D_(iN).sbsb.i and the current bypassing resistors R_(il) to R_(iN).sbsb.i respectively connected in parallel with the diodes D_(il) to D_(iN).sbsb.i and a light emitting diode D_(i0) connected in series with the diode circuit G_(i) ; the unit circuits M₁ to M.sub.(P-1) have respectively the current detecting circuits F₁ to F.sub.(p-1) which are connected in series with the diode circuits G₁ to G.sub.(p-1), respectively; and the unit circuits M₂ to M_(P) have the current control circuits H₂ to H_(P) which are connected in series with the diode circuits G₂ to G_(p), respectively and controlled by the current detecting circuits F to F.sub.(p-1), respectively. According to the present invention, it is possible to display the level of the input signal S with such a simple circuit arrangement. Accordingly, the level meter circuit of the present invention can be made small, simple and inexpensive. Further, by increasing the number P of the unit circuits M₁ to M_(P) without increasing the number N_(i) of the diodes D_(il) to D_(iN).sbsb.i in the diode circuit G_(i) of the unit circuit M_(i), the level of the input signal S can be displayed over a wider range. This means that the diodes are all lighted at the same brightness. Accordingly, there can be produced a visually beautiful display of the level of the input signal S.

The foregoing embodiment should be construed as being merely illustrative of the present invention. For example, in the illustrated arrangement of the level meter circuit of the present invention, the diodes D₂₀ to D_(P0) of the unit circuits M₂ to M_(P) can be omitted. Also it is possible to leave out the diode D₁₀ in the unit circuit M₁.

In the foregoing it has been described that as the current I_(S) flowing in the parallel circuit 1 sequentially increases by the same amount of level, the currents I₂, I₃, . . . I_(P) respectively flow in the unit circuits M₂, M₃, . . . M_(P) in a sequential order, and that the currents I₁, I₂, . . . I_(P) flowing in the unit circuits M₁, M₂, . . . M_(P) assume the same saturation level. It is also possible, however, that by suitably arranging the current detecting circuits F₁ to F.sub.(P-1) and the current control circuits H₂ to H_(P), as the current I_(S) sequentially increases by an amount of level different from that of the immediately previous current increase, the currents I₂, I₃, . . . I_(P) respectively flow in the unit circuits M₂, M₃, . . . M_(P) in a sequential order, and that the currents I₁ , I₂, . . . I_(P) assume different saturation levels. Further, it has been described in the foregoing that each time the current I_(i) sequentially increases by the same amount of level, the diodes D_(i0), D_(i1), . . . D_(iN).sbsb.i in the unit circuit M_(i) are each lighted in a sequential order by suitably selecting the values r_(i1) to r_(iN).sbsb.1 of the the resistors R_(i1) to R_(iN).sbsb.1 within the range that satisfies the equation (6). It is also possible, however, that each time the current I_(i) increases by an amount of level different from that of the immediately previous current increase, the abovesaid diodes are each lighted in a sequential order.

It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention. 

What is claimed is:
 1. A level meter circuit comprising:a parallel circuit of P unit circuits M₁, M₂, . . . M_(p) ; and main current control means connected in series with the parallel circuit and controlled by an input signal the level of which is to be displayed; wherein the unit circuit M_(i) (i=1, 2, . . . P) has a diode circuit G_(i), the diode ciruit G_(i) having N_(i) series-connected light emitting diodes D_(i1), D_(i2), . . . D_(iN).sbsb.i and current bypassing resistors R_(i1), R_(i2), . . . R_(iN).sbsb.i respectively connected in parallel with the light emitting diodes D_(i1), D_(i2), . . . D_(iN).sbsb.i, and the current bypassing resistors R_(i1), R_(i2), . . . R_(iN).sbsb.i having smaller resistance values in this order; wherein the unit circuits M₁ to M.sub.(P-1) respectively have current detecting circuits F₁ to F.sub.(P-1) which are connected in series with the diode circuits G₁ to G.sub.(P-1), respectively; and wherein the unit circuits M₂ to M_(P) respectively have current control circuits M₂ to M_(P) which are connected in series with the diode circuits G₂ to G_(P) respectively and controlled by the current detecting circuits F₁ to F.sub.(P-1) respectively.
 2. A level meter circuit according to claim 1 wherein the unit circuit M₁ has a light emitting diode D₁₀ connected in series with the diode circuit G₁.
 3. A level meter circuit according to claim 1 wherein the main current control means has a current control transistor connected in series with the parallel circuit.
 4. A level meter circuit according to claim 1 wherein the unit circuits M₂ to M_(P) respectively have light emitting diodes D₂₀ to D_(P0) which are connected in series with the diode circuits G₂ to G_(P), respectively.
 5. A level meter circuit according to claim 1 wherein the current detecting circuits F₁ to F.sub.(P-1) respectively have current detecting resistors R₁₀ to R.sub.(P-1)0 which are connected in series with the diode circuits G₁ to G.sub.(P-1), respectively.
 6. A level meter circuit according to claim 1 wherein the current control circuits H₂ to H_(P) have current control transistors Q₂ to Q_(P) which are connected in series with the diodes circuits G₂ to G_(P), respectively. 